課程資訊
課程名稱
 電子設計自動化導論
Introduction to Electronic Design Automation 
開課學期
 110-2 
授課對象
 電機資訊學院  電機工程學系  
授課教師
 江介宏 
課號
 EE3012 
課程識別碼
 901 33700 
班次
  
學分
 3.0 
全/半年
 半年 
必/選修
 選修 
上課時間
 星期五7,8,9(14:20~17:20) 
上課地點
 電二106 
備註
 總人數上限：60人 
  
課程簡介影片
 
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課程概述

1. Introduction

History, VLSI design flow, etc.

2. Basics of Computation Theory and Mathematical Optimization

3. Models of computation

Finite state machine, finite automata, Kahn process network, Petri net, neural network, etc.

4. High-level synthesis

Design space exploration, resource sharing, etc.

5. Logic synthesis

Technology independent optimization, technology mapping, technology dependent optimization, timing and power analysis, etc.

6. Verification

Combinational and sequential equivalence checking, property checking, etc.

7. Physical design

Floorplanning, placement, routing, etc.

8. Testing

Combinational and sequential ATPG, design for test, etc.

9. Advanced topics

Neural network synthesis, quantum circuit synthesis and simulation, etc.
 

課程目標
 Electronic Design Automation (EDA) concerns the correctness, reliability, productivity, and optimization of system construction. It is an interdisciplinary field, where electrical engineering and computer sciences intersect. In EDA, theoretical computer science (including algorithms, complexity, automata, logic, programming languages, etc.) finds rich and practical applications. On the other hand, some of the techniques developed in the EDA community have been much enhanced the state-of-the-art solvers on intractable problems. In this course we will study some representative problems and solutions making VLSI design an automatic process. In particular, we will cover system modeling, optimization, analysis, and verification.  
課程要求
 Prerequisite:
Switching circuits and logic design  
預期每週課後學習時數
  
Office Hours
  
指定閱讀
 Course handouts 
參考書目
 Textbook：
Electronic Deisng Automation: Synthesis, Verification, and Test, Laung-Terng Wang, Kwang-Ting (Tim) Cheng, and Yao-Wen Chang, editors, Morgan Kaufmann Publishers, 2009.
 
評量方式
(僅供參考)
  
No.
項目
百分比
說明
1. 
 Participation 
3% 
  
2. 
 Final Project 
25% 
 CAD Contest participation (recommended) 
3. 
 Final Quiz 
10% 
  
4. 
 Midterm Exam 
30% 
  
5. 
 Homework 
32% 
 4 assignments 
 
課程進度
週次
日期
單元主題
第1週
 2/18  Introduction 
第2週
 2/25  Computation and Optimization 
第3週
 3/4  Models of Computation

 
第4週
 3/11  High-Level Synthesis 
第5週
 3/18  Logic Synthesis (1)
 
第6週
 3/25  Logic Synthesis (2) 
第7週
 4/1  Verification (1)  
第8週
 4/8  Midterm 
第9週
 4/15  Verification (2) 
第10週
 4/22  Physical Design (1)  
第11週
 4/29  Physical Design (2)  
第12週
 5/6  Testing (1) 
第13週
 5/13  Testing (2) 
第14週
 5/20  Advanced Topics (1) 
第15週
 5/27  Advanced Topics (2) 
第16週
 6/3  Dragon Boat Festival 
第17週
 6/10  Advanced Topics (3) 
第18週
 6/17  Final Project Presentation